module crc(//input
			clk,
			rst_n,
			oe,
			din,
			rst,
		   //output
		    dout
			);
input        clk,
		     rst_n,
			 rst,
			 oe,
			 din;
output[15:0] dout;

reg[15:0]    lsfr;

assign dout = lsfr;

always @(posedge clk or negedge rst_n)
    if(rst_n == 1'b0) begin
	    lsfr <= 16'h0000;
	end
	else if(~rst) begin
		lsfr <= 16'h0000;
	end
	else if(~oe) begin
		lsfr <= lsfr;
	end
	else begin
		lsfr[15] <= lsfr[14];
		lsfr[14] <= lsfr[13];
		lsfr[13] <= lsfr[12];
		lsfr[12] <= lsfr[11] ^ lsfr[15] ^ din;
		lsfr[11] <= lsfr[10];
		lsfr[10] <= lsfr[9];
		lsfr[9] <= lsfr[8];
		lsfr[8] <= lsfr[7];
		lsfr[7] <= lsfr[6];
		lsfr[6] <= lsfr[5];
      	lsfr[5] <= lsfr[4] ^ lsfr[15] ^din;
		lsfr[4] <= lsfr[3];
		lsfr[3] <= lsfr[2];
		lsfr[2] <= lsfr[1];
		lsfr[1] <= lsfr[0];
		lsfr[0] <= lsfr[15] ^ din;
	end

endmodule
